1. Field of the Invention
This invention concerns oscillator circuitry, and more particularly concerns oscillator circuitry having a number of inverters operating in a ring.
2. Related Art
Oscillators are used in a wide range of applications, notably including clocks for processors. Processors in turn are increasingly used in a wide range of small devices for which economy of power consumption is desired, including cell phones, cameras, audio equipment, personal digital assistants and notebook computers. Reducing clock speed is an important capability for reducing power consumption.
In recent years processor clock speeds have increased so dramatically that there is a lot of room for reducing speed to achieve reduced power consumption while still having sufficient speed, at least in some circumstances, for substantial processing capability. An example of an oscillator design with a number of inverters operating in a ring and which achieves a range of frequency operation is U.S. patent application Ser. No. 09/974,969 xe2x80x9cMulti-Mode VCO,xe2x80x9d filed Oct. 11, 2001, which is hereby incorporated herein by reference. However, even with the Multi-Mode VCO design it may not be possible to turn down clock speed to the extent which processing capability and application requirements may permit, particularly since the number of inverters in the basic oscillating loop remains fixed in at least one respect. Consequently, a need exists for improvements in variable frequency oscillator operation.
The foregoing need is addressed in the present invention. According to an apparatus form of the invention, oscillator circuitry for operating a number of inverters in a loop (also known as a xe2x80x9cringxe2x80x9d) includes a number of inverters. The inverters include a series of M inverters and a series of N inverters. The M inverters have signal propagation delay of m and the N inverters have signal propagation delay of n. The circuitry also includes means for selecting whether to exclude the N inverters from operating in the loop, which includes receiving a select signal on a data input of the selecting means. The selecting means times assertion of the select signal on an output to select the number of inverters. In order to glitchlessly change the number of inverters operating in the loop, the assertion of the select signal is delayed by a certain delay greater than delay n.
In another aspect, the select signal is asserted the certain delay after a falling edge of the Mth inverter""s output signal. Also, the selecting means includes a multiplexer having a certain switching delay, and in order to further ensure glitchless operation the certain delay is small enough such that select signal is asserted on the selecting means output at least the multiplexer switching delay before a next rising edge of the Mth inverter output signal.